OI!STER: Difference between revisions

Revision as of 11:46, 18 August 2021

The OI!STER is an STM32L5 Target Board with a QFP48 clamshell socket aimed at debugging and glitching salvaged MCUs. The board can be powered via USB-C, a 2032 coin cell battery on the back of the board or an external power suppy. All pins are broken out in the 24-pin headers on either side at the top of the board. The OI!STER contains five debug headers, to support a wide range of debugging hardware such as a Hydrabus or a Black Magic Probe. It comes with six SMA connectors arranged in I/O pairs. One pair is dedicated to glitching the external LSE clock, another for glitching the external HSE clock and one pair for power analysis and fault injection with a Chipwhisperer. Each SMA connector can be bypassed by removing a small jumper. The OI!STER also has additional solder jumpers for the external clocks and each of the power traces to the MCU to allow for quick experimentation.

A full pinout and additional documentation is currently under development.

LPUART/USART/UART/USB/SWD/JTAG/USB/OSC/OSC32 Pinout


LPUART/USART/UART/SWD/JTAG/USB/OSC/OSC32 Pinout


Pin	Function	Alternate Function
1	VBAT
2	PC13
3	PC14	OSC32_IN
4	PC15	OSC32_OUT
5	PH0	OSC_IN
6	PH1	OSC_OUT
7	NRST
8	VSSA	VREF-
9	VDDA	VREF+
10	PA0	UART4_TX	USART2_CTS
11	PA1	UART4_RX	USART2_RTS
12	PA2	LPUART1_TX	USART2_TX
13	PA3	LPUART1_RX	USART2_RX
14	PA4	USART2_CK
15	PA5
16	PA6	LPUART1_CTS	USART3_CTS
17	PA7
18	PB0	LED1	USART3_CK
19	PB1	LED2	LPUART1_RTS	USART3_RTS
20	PB2
21	PB10	LPUART1_RX	USART3_TX
22	PB11	LPUART1_TX	USART3_RX
23	VSS
24	VDD
25	PB12	USART3_CK	LPUART1_RTS
26	PB13	USART3_CTS	LPUART1_CTS
27	PB14	USART3_RTS
28	PB15
29	PA8	USART1_CK
30	PA9	USART1_TX
31	PA10	USART1_RX
32	PA11	USART1_CTS	USB_DM
33	PA12	USART1_RTS	USB_DP
34	PA13	JTMS	SWDIO	USB_NOE
35	VSS_2
36	VDD_2
37	PA14	JTCK	SWCLK
38	PA15	JTDI	USART2_RX	USART3_RTS	UART4_RTS
39	PB3	JTDO	TRACESWO	USART1_RTS
40	PB4	NJTRST	USART1_CTS
41	PB5	USART1_CK
42	PB6	USART1_TX
43	PB7	USART1_RX	UART4_CTS
44	PH3	BOOT0
45	PB8
46	PB9
47	VSS_3
48	VDD_3

LPUART1


Pin		Function
12	22	LPUART1_TX
13	21	LPUART1_RX
16	26	LPUART1_CTS
19	25	LPUART1_RTS

USART1


Pin		Function
29	41	USART1_CK
30	42	USART1_TX
31	43	USART1_RX
32	40	USART1_CTS
33	39	USART1_RTS

USART2


Pin		Function
10		USART2_CTS
11		USART2_RTS
12		USART2_TX
13	38	USART2_RX
14		USART2_CK

USART3


Pin		Function
16	26	USART3_CTS
18	25	USART3_CK
19	27	USART3_RTS
21		USART3_TX
22		USART3_RX

UART4


Pin	Function
10	UART4_TX
11	UART4_RX
38	UART4_RTS
43	UART4_CTS

SWD


Pin	Function
7	NRST
34	SWDIO
37	SWCLK
38	NC
39	TRACESWO

JTAG


Pin	Function
34	JTMS
37	JTCK
38	JTDI
39	JTDO
40	NJTRST

USB


Pin	Function
32	USB_DM
33	USB_DP
34	USB_NOE

OSC


Pin	Function
5	OSC_IN
6	OSC_OUT

OSC32


Pin	Function
3	OSC32_IN
4	OSC32_OUT

I2C/SPI/OCTOSPI/FDCAN/SDMMC Pinout


I2C/SPI/OCTOSPI/FDCAN/SDMMC Pinout


Pin	Function	Alternate Function
1	VBAT
2	PC13
3	PC14
4	PC15
5	PH0
6	PH1
7	NRST
8	VSSA
9	VDDA
10	PA0
11	PA1	I2C1_SMBA	SPI1_SCK	OCTOSPI1_DQS
12	PA2	OCTOSPI1_NCS
13	PA3	OCTOSPI1_CLK
14	PA4	SPI1_NSS	SPI3_NSS	OCTOSPI1_NCS
15	PA5	SPI1_SCK
16	PA6	SPI1_MISO	OCTOSPI1_IO3
17	PA7	I2C3_SCL	SPI1_MOSI	OCTOSPI1_IO2
18	PB0	SPI1_NSS	OCTOSPI1_IO1
19	PB1	OCTOSPI1_IO0
20	PB2	I2C3_SMBA	OCTOSPI1_DQS
21	PB10	I2C2_SCL	I2C4_SCL	SPI2_SCK	OCTOSPI1_CLK
22	PB11	I2C2_SDA	I2C4_SDA	OCTOSPI1_NCS
23	VSS
24	VDD
25	PB12	I2C2_SMBA	SPI2_NSS	OCTOSPI_NCLK
26	PB13	I2C2_SCL	SPI2_SCK
27	PB14	I2C2_SDA	SPI2_MISO
28	PB15	SPI2_MOSI
29	PA8
30	PA9	SPI2_SCK
31	PA10
32	PA11	SPI1_MISO	FDCAN1_RX
33	PA12	SPI1_MOSI	FDCAN1_TX
34	PA13
35	VSS_2
36	VDD_2
37	PA14	I2C1_SMBA	I2C4_SMBA
38	PA15	SPI1_NSS	SPI3_NSS
39	PB3	SPI1_SCK	SPI3_SCK
40	PB4	I2C3_SDA	SPI1_MISO	SPI3_MISO
41	PB5	I2C1_SMBA	SPI1_MOSI	SPI3_MOSI	OCTOSPI_NCLK
42	PB6	I2C2_SCL	I2C4_SCL
43	PB7	I2C1_SDA	I2C4_SDA
44	PH3
45	PB8	I2C1_SCL	FDCAN1_RX	SDMMC1_CKIN	SDMMC1_D4
46	PB9	I2C1_SDA	SPI2_NSS	FDCAN1_TX	SDMMC1_CDIR	SDMMC1_D5
47	VSS_3
48	VDD_3

I2C1


Pin		Function
11	41	I2C1_SMBA
43	46	I2C1_SDA
42	45	I2C1_SCL

I2C2


Pin		Function
21	26	I2C2_SCL
22	27	I2C2_SDA
25		I2C2_SMBA

I2C3


Pin	Function
17	I2C3_SCL
25	I2C3_SMBA
40	I2C3_SDA

I2C4


Pin		Function
21	42	I2C4_SCL
22	43	I2C4_SDA
37		I2C4_SMBA

SPI1


Pin			Function
11	15	39	SPI1_SCK
14	18	38	SPI1_NSS
16	32	40	SPI1_MISO
17	33	41	SPI1_MOSI

SPI2


Pin		Function
21	26	SPI2_SCK
25		SPI2_NSS
27		SPI2_MISO
28		SPI2_MOSI

SPI3


Pin		Function
14	38	SPI3_NSS
39		SPI3_SCK
40		SPI3_MISO
41		SPI3_MOSI

OCTOSPI1


Pin		Function
11	20	OCTOSPI1_DQS
12	14	OCTOSPI1_NCS
13	21	OCTOSPI1_CLK
16		OCTOSPI1_IO3
17		OCTOSPI1_IO2
18		OCTOSPI1_IO1
25	41	OCTOSPI1_NCLK

FDCAN


Pin	Function
32	FDCAN_RX
33	FDCAN_TX

SDMMC


Pin	Function
45	SDMMC1_CKIN
46	SDMMC_CDIR
45	SDMMC_D4
46	SDMMC_D5

@@ Line 8: / Line 8: @@
 <br><br>
-== '''LPUART/USART/UART/SWD/JTAG/OSC/OSC32 Pinout''' ==
+== '''LPUART/USART/UART/USB/SWD/JTAG/USB/OSC/OSC32 Pinout''' ==
 {| class="wikitable"
 |+
-!  scope="row" | LPUART/USART/UART/SWD/JTAG/OSC/OSC32 Pinout
+!  scope="row" | LPUART/USART/UART/SWD/JTAG/USB/OSC/OSC32 Pinout
 |-
 | [[File:OISTER Pinout DBG-50.png|2000px]]
@@ Line 397: / Line 397: @@
 ! scope="row" | 40
 | NJTRST
+|}
+=== USB ===
+{| class="wikitable"
+|+
+! scope="col" colspan="1"| Pin
+! scope="col" colspan="2"| Function
+|-
+! scope="row" | 32
+| USB_DM
+|-
+! scope="row" | 33
+| USB_DP
+|-
+! scope="row" | 34
+| USB_NOE
 |}